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Overview
Systems built with CES boards
may include several configurable hardware
components using FPGAs located on processor boards, MFCCs and GPIOs.
CES provides a complete environment to generate and deploy
user-specific applications on these configurable
components. This environment is called the CES FPGA Board Support
Package (BSP). It has been developed with the main goal of making
possible the evaluation, simulation and integration of user
applications in most CES FPGA-based platforms, in an intuitive, optimal
and fast manner. The user application is implemented within a container
entity in the FPGA superstructure, which is referred to as the CES User
Isle.
Hardware
and Software Support
The CES FPGA BSP consists of
the following components:
- FPGA superstructure including
CES pre-compiled IP's (ex.
memory controllers, PCI / PCIe interfaces, DMA engine, interrupt
controller)
- Interconnect with FPGA
superstructure
- Low-latency connection with an
external processor (where
applicable)
- System-wide connectivity
though high-speed serial link
interfaces (where applicable)
- Full simulation environment of
the user application
(scripts, bus functional models for CES User Isle interfaces)
- Design flow scripts (FPGA
bitstream generation scripts)
- A collection of design
examples and application-specific IPs
- A ready-to-use User Isle
example
- Utilities and drivers
(ex. to manage the storage of several
FPGA
bitstreams and user-initiated FPGA reconfiguration)
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CES USER ISLE
Integration
with High-Level Tools
The
CES FPGA BSP enables different approaches for application design,
without
imposing a unique design entry for the CES User Isle. It is intended to
be used by engineers with different levels of expertise in FPGA design,
ranging
from experts to developers having little or no knowledge about HDL
languages. As a result, the user can concentrate on the complexity of
the application and avoid the burden of the integration process.
Most of CES fourth and fifth generation products are now equipped
with
large FPGAs (Xilinx Virtex II Pro, Virtex 5), which support external
PowerPC
processors, control board resources and host user-specific
applications within the CES User Isle.
CES
User Isle
CES provides the synthesized FPGA infrastructure, including all of the
relevant CES IPs, ready to integrate the User Isle. This, in turn,
is developed and synthesized independently by the user. The two are
combined during the place and route process and are supported by
configuration and constraint files provided by CES. The user must
conform to the port map of the User Isle specified by CES, but
otherwise can
retain complete control of the internal structure of the User Isle,
including the synthesis process. While the available resources in the
products may be different, the User Isle interface for each resource is
independent of the actual product. Thus, it is easy to move the design
from one product to another, as long as the required resources are
available.
The CES User Isle is directly coupled to the IP interconnect of the the
FPGA superstructure. Thus, the User Isle can be accessed by the
external
processors or from external agents, such as VME or PCI, through a
simple
memory map. Where applicable, the User Isle is also directly connected
to
external memory controllers such as DDR2, RLDRAM or QDRII memory
controllers.
The external memory controller interface is unified, enabling the user
to migrate the application transparently from one memory type to
another, if required.
The CES User Isle features the following:
- Clock and reset port to synchronize the user application
with the rest of the FPGA superstructure
- Master and slave port to the IP interconnect of the FPGA
superstructure
- Unified interface with external memory controller
- User I/Os
- Interrupt port to external processors
- A ready-to-use User Isle example (basic register mapping
and interrupt generation)
- A collection of more advanced User Isle examples (including
use of embedded CPU cores)
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FPGA BSPs
